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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 tps4019x 4.5-v to 18-v input, 10-pin, synchronous buck controller with power good 1 1 features 1 ? input operating voltage range: 4.5 v to 18 v ? up to 20-a output currents ? supports pre-biased outputs ? 0.5%, 591-mv reference ? switching frequency ? tps40192: 600 khz ? tps40193: 300 khz ? three selectable thermally compensated short- circuit protection levels ? hiccup restart from faults ? internal 5-v regulator ? high-side and low-side mosfet on-resistance (r ds(on) ) current sensing ? 10-pin 3 mm 3 mm son package ? internal 4-ms soft-start time ? thermal shutdown protection at 145 c 2 applications ? cable modem cpe ? digital set top box ? graphics/audio cards ? entry level and mid-range servers 3 description tps40192 and tps40193 are cost-optimized synchronous buck controllers that operate from 4.5 v to 18 v input. these controllers implement a voltage- mode control architecture with the switching frequency fixed at either 600 khz (tps40192) or 300 khz (tps40193). the higher switching frequency facilitates the use of smaller inductor and output capacitors, thereby providing a compact power- supply solution. an adaptive anti-cross conduction scheme is used to prevent shoot through current in the power fets. short circuit detection is done by sensing the voltage drop across the low-side mosfet when it is on and comparing it with a user selected threshold of 100 mv, 200 mv or 280 mv. the threshold is set with a single external resistor connected from comp to gnd. this resistor is sensed at startup and the selected threshold is latched. pulse-by-pulse limiting (to prevent current runaway) is provided by sensing the voltage across the high-side mosfet when it is on and terminating the cycle when the voltage drop rises above a fixed threshold of 550 mv. when the controller senses an output short circuit, both mosfets are turned off and a timeout period is observed before attempting to restart. this behavior provides limited power dissipation in the event of a sustained fault. device information (1) part number package body size (nom) tps40192 vson (10) 3.00 mm 3.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified application diagram 1 2 3 4 10 9 8 7 hdrv sw boot ldrv enable fb comp vdd tps40192 tps401923 5 6 bp5 pgd 11 gnd v in v out on/ off external logic supply 5-v or less or bp5 v out copyright ? 2016, texas instruments incorporated +3.3v pgd productfolder ordernow technical documents tools & software support &community referencedesign
2 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 dissipation ratings ................................................... 6 6.7 typical characteristics .............................................. 7 7 detailed description .............................................. 9 7.1 overview ................................................................... 9 7.2 functional block diagram ......................................... 9 7.3 feature description ................................................... 9 7.4 device functional modes ........................................ 14 8 application and implementation ........................ 15 8.1 application information ............................................ 15 8.2 typical application ................................................. 15 9 power supply recommendations ...................... 23 10 layout ................................................................... 24 10.1 layout guidelines ................................................. 24 10.2 layout examples ................................................... 24 11 device and documentation support ................. 26 11.1 device support ...................................................... 26 11.2 documentation support ........................................ 27 11.3 related links ........................................................ 27 11.4 receiving notification of documentation updates 27 11.5 community resources .......................................... 27 11.6 trademarks ........................................................... 27 11.7 electrostatic discharge caution ............................ 27 11.8 glossary ................................................................ 27 12 mechanical, packaging, and orderable information ........................................................... 27 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision e (may 2013) to revision f page ? added pin configuration and functions section, esd rating table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section .............................. 1 changes from revision d (july 2012) to revision e page ? added clarity to figure 15 ..................................................................................................................................................... 15 ? added note regarding high-resistance resistor. .................................................................................................................... 19 changes from revision c (august 2010) to revision d page ? added text to the last paragraph in the enable functionality section. ................................................................................. 10 changes from revision b (september 2007) to revision c page ? changed corrected label for pin 8 .......................................................................................................................................... 3 ? changed corrected waveform .............................................................................................................................................. 11
3 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 5 pin configuration and functions drc package 10-pin vson top view pin functions pin i/o description name no. boot 8 i gate drive voltage for the high-side n-channel mosfet. a capacitor 100 nf typical must be connected between this pin and sw. bp5 6 o output bypass for the internal regulator. connect a capacitor with a value of at least 1- f from this pin to gnd. larger capacitors (up to 4.7- f) can improve noise performance when using a low-side mosfet with a gate charge of 25 nc or greater. low power, low noise loads may be connected here if desired. the sum of the external load and the gate drive requirements must not exceed 50 ma. this regulator is turned off when enable is pulled low. comp 3 o output of the error amplifier. enable 1 i logic level input which starts or stops the controller from an external user command. a high-level turns the controller on. a weak internal pull-up holds this pin high so that the pin may be left floating if this function is not used. fb 2 i inverting input to the error amplifier. in normal operation the voltage on this pin is equal to the internal reference voltage (591 mv typical) hdrv 10 o bootstrapped output for driving the gate of the high-side n-channel fet. ldrv 7 o output to the rectifier mosfet gate pgd 5 o open drain power good output sw 9 i sense line for the adaptive anti-cross conduction circuitry. serves as common connection for the flying high- side mosfet driver vdd 4 i power input to the controller thermal pad g common reference for the device. connect to the system gnd. enable 12 34 5 fb comp vdd pgd 10 9 87 6 hdrv sw boot ldrv bp5 thermal pad
4 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (1) stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operating conditions " is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range unless otherwise noted (1) min max unit input voltage vdd, enable ? 0.3 20 v sw ? 5 25 boot, hdrv ? 0.3 30 boot-sw, hdrv-sw (differential from boot or hdrv to sw) ? 0.3 6 comp, fb, bp5, ldrv, pgd ? 0.3 6 operating junction temperature, t j ? 40 150 c storage temperature, t stg ? 55 150 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2500 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 1500 6.3 recommended operating conditions min max unit v vdd input voltage 4.5 18 v t j operating junction temperature -40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 6.4 thermal information thermal metric (1) tps40192 unit drc (vson) 10 pins r ja junction-to-ambient thermal resistance 46.4 c/w r jc(top) junction-to-case (top) thermal resistance 51.4 c/w r jb junction-to-board thermal resistance 21.8 c/w jt junction-to-top characterization parameter 0.9 c/w jb junction-to-board characterization parameter 22.0 c/w r jc(bot) junction-to-case (bottom) thermal resistance 6.6 c/w
5 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (1) specified by design. not production tested. 6.5 electrical characteristics t j = ? 40 c to 85 c, v vdd = 12 v dc , all parameters at zero power dissipation (unless otherwise noted) parameter test conditions min typ max unit reference v fb feedback voltage range 0 c t j 85 c 588 591 594 mv -40 c t j 85 c 585 591 594 input supply v vdd input voltage range 4.5 18 v i vdd operating current v enable = 3 v 2.5 4 ma v enable = 0.6 v 45 70 a on board regulator v 5vbp output voltage v vdd > 6 v, i 5vbp 10 ma 5.1 5.3 5.5 v v do regulator dropout voltage v vdd - v bp5 , v vdd = 5 v, i bp5 25 ma 350 550 mv i sc regulator current limit threshold 50 ma i bp5 average current 50 oscillator f sw switching frequency tps40193 240 300 360 khz tps40192 500 600 700 v rmp ramp amplitude (1) 1 v pwm d max maximum duty cycle (1) 85% t on(min) minimum controlled pulse (1) 110 ns t dead output driver dead time hdrv off to ldrv on 50 ldrv off to hdrv on 25 soft-start t ss soft-start time 3 4 6 ms t ssdly soft-start delay time 2 t reg time to regulation 6 error amplifier gbwp gain bandwidth product (1) 7 10 mhz a ol dc gain (1) 60 db i ib input bias current (current out of fb pin) 100 na i eaop output source current v fb = 0 v 1 ma i eaom output sink current v fb = 2 v 1 short circuit protection t pss(min) minimum pulse during short circuit (1) 250 ns t blnk blanking time (1) 60 90 120 t off off-time between restart attempts 30 50 ms v ilim short circuit comparator threshold voltage r comp(gnd) = open, t j = 25 c 160 200 240 mv r comp(gnd) = 4 k ? , t j = 25 c 80 100 120 r comp(gnd) = 12 k ? , t j = 25 c 228 280 342 v ilimh short circuit threshold voltage on high- side mosfet t j = 25 c 400 550 650
6 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated electrical characteristics (continued) t j = ? 40 c to 85 c, v vdd = 12 v dc , all parameters at zero power dissipation (unless otherwise noted) parameter test conditions min typ max unit output drivers r hdhi high-side driver pull-up resistance v boot - v sw = 4.5 v, i hdrv = -100 ma 3 6 ? r hdlo high-side driver pull-down resistance v boot - v sw = 4.5 v, i hdrv = 100 ma 1.5 3.0 r ldhi low-side driver pull-up resistance i ldrv = -100 ma 2.5 5.0 r ldlo low-side driver pull-down resistance i ldrv = 100 ma 0.8 1.5 t hrise high-side driver rise time (1) c load = 1 nf 15 35 ns t hfall high-side driver fall time (1) 10 25 t lrise low-side driver rise time (1) 15 35 t lfall low-side driver fall time (1) 10 25 uvlo v uvlo turn-on voltage 3.9 4.2 4.4 v uvlo hyst hysteresis 700 800 900 mv shutdown v ih high-level input voltage, enable 1.9 3 v v il low-level input votlage, enable 0.6 power good v ov feedback voltage limit for powergood 650 mv v uv feedback voltage limit for powergood 525 v pg_hyst powergood hysteresis voltage at fb pin 30 r pgd pulldown resistance of pgd pin v fb = 0 v 7 50 ? i pdglk leakage current v fb = 0 v 7 12 a boot diode v dfwd bootstrap diode forward voltage i boot = 5 ma 0.5 0.8 1.2 v thermal shutdown t jsd junction shutdown temperature (1) 145 c t jsdh hysteresis (1) 20 (1) ratings based on jedec high thermal conductivity (high k) board. for more information on the test method, see ti technical brief szza017 . 6.6 dissipation ratings package airflow (lfm) r ja high-k board (1) ( c/w) power rating (w) t a = 25 c power rating (w) t a = 85 c drc 0 (natural convection) 47.9 2.08 0.835 200 40.5 2.46 0.987 400 38.2 2.61 1.04
7 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 6.7 typical characteristics figure 1. relative reference feedback voltage vs junction temperature figure 2. relative oscillator frequency change vs junction temperature v enable < 0.6 v figure 3. shutdown input current vs junction temperature figure 4. enable threshold voltage vs junction temperature figure 5. soft-start time vs junction temperature figure 6. low-side mosfet current limit threshold vs junction temperature 0 10 20 30 40 50 60 40 25 10 5 20 35 95 50 65 80 110 125 shutdown current (a) junction temperature (c) 0 0.5 1.0 1.5 2.0 2.5 40 25 10 5 20 35 95 125 50 65 80 110 turn-on turn-off junction temperature (c) enable threshold voltage (v) 40 25 10 5 20 35 95 125 4.5 4.0 3.5 1.5 1.0 0.5 0.5 3.0 2.5 2.0 0.0 50 65 80 110 junction temperature (c) rel oscillator frequency change (%) 40 25 10 5 20 35 95 125 50 65 80 110 0.50 0.45 0.40 0.20 0.15 0.05 0.35 0.30 0.25 0.00 0.50 0.10 junction temperature (c) rel reference voltage change (%) 40 25 10 5 20 35 95 125 50 65 80 110 0 50 150 200 250 350 400 100 300 r comp ( n? ) 12 4 open junction temperature (c) current limit threshold (mv) 3.75 3.80 3.85 3.90 3.95 4.00 4.05 40 25 10 5 20 35 95 125 50 65 80 110 junction temperature (c) soft-start time (ms)
8 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated typical characteristics (continued) figure 7. high-side mosfet current limit threshold vs junction temperature figure 8. total time to regulation vs junction temperature figure 9. powergood threshold voltage vs junction temperature figure 10. shutdown current vs input voltage figure 11. relative overcurrent trip point vs freewheel time 0 1 2 3 4 5 0.4 0.6 0.8 1.0 1.6 1.2 1.4 freewheel time (s) relative overcurrent trip point (a) 1.5 2.5 3.5 4.5 0.5 560 580 540 520 500 660 680 640 620 600 40 25 10 5 20 35 95 125 50 65 80 110 junction temperature (c) overvoltage undervoltage powergood threshold voltage (mv) 0 20 40 60 80 100 4 6 8 10 18 12 14 16 input voltage (v) supply current (a) 30 50 70 90 10 0 100 300 400 600 700 800 500 200 40 25 10 5 20 35 95 125 50 65 80 110 junction temperature (c) high-side mosfet current limit threshold (mv) 4.4 5.3 5.7 6.1 6.3 5.5 4.7 4.9 5.1 5.5 5.9 40 25 10 5 20 35 95 125 50 65 80 110 junction temperature (c) regulation time (ms)
9 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 7 detailed description 7.1 overview the tps40192 and tps40193 devices are cost optimized controllers providing all the necessary features to construct a high performance dc/dc converter while keeping costs to a minimum. support for pre-biased outputs eliminates concerns about damaging sensitive loads during startup. strong gate drivers for the high-side and rectifier n-channel mosfets decrease switching losses for increased efficiency. adaptive gate drive timing prevents shoot through and minimizes body diode conduction in the rectifier mosfet, also increasing efficiency. selectable short circuit protection thresholds and hiccup recovery from a short circuit increase design flexibility and minimize power dissipation in the event of a prolonged output fault. the dedicated enable pin allows the converter to be placed in a very low quiescent current shutdown mode. internally fixed switching frequency and soft-start time reduce external component count, simplifying design and layout, as well as reducing footprint and cost. the 3 mm 3 mm package size also contributes to a reduced overall converter footprint. 7.2 functional block diagram 7.3 feature description 7.3.1 voltage reference the band gap cell is designed with a trimmed 591-mv output. the 0.5% tolerance on the reference voltage allows the user to design a very accurate power-supply. 7.3.2 oscillator the tps40192 has a fixed internal switching frequency of 600 khz. tthe tps40193 operates at a switching frequency of 300 khz. enable 1 vdd 4 bp5 6 comp 3 fb 2 thermal pad 5 v regulator 4.2 v + 5 v uvlo + error amplifier 591 mv ss + fault controller soft start ramp generator pwm logic and anti-cross conduction + (v vdd 0.5 v) oscillator short circuit threshold selector sd uvlo uvlo ss sd fault uvlo + clk 10 clk 8 7 9 5 boot hdrv sw ldrv pgd 5 v powergood control fb sd fault 5 v sc threshold latch sc: 110 mv, 200 mv, or 280 mv 750 k : vdd sc sd + fault ocl och copyright ? 2016, texas instruments incorporated
10 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated feature description (continued) 7.3.3 uvlo when the input voltage is below the uvlo threshold, the device holds all gate drive outputs in the low (off) state. when the input rises above the uvlo threshold, and the enable pin is above the turn on threshold, the oscillator begins to operate and the start-up sequence is allowed to begin. the uvlo level is internally fixed at 4.2 v. 7.3.4 enable functionality a dedicated enable pin simplifies a user-level interface design where no multiplexed functions exist. another benefit is a true low power shutdown mode of operation. when the enable pin is pulled to gnd, all unnecessary functions, including the bp5 regulator, are turned off, reducing the device supply (i dd ) current to 45- a. a functionally equivalent circuit of the enable circuitry shown in figure 12 . figure 12. enable pin internal circuitry if the enable pin is left floating, the chip starts automatically. the pin must be pulled to less than 600 mv to ensure that the tps40192 and tps40193 devices is in shutdown mode. note that the enable pin is relatively high impedance. some applications generate enough nearby noise to cause the enable pin to swing below the 600 mv threshold and give an erroneous shutdown commands to the rest of the device. there are two solutions to solve this problem. 1. place a capacitor from enable to gnd. a side effect of this is to delay the start of the converter while the capacitor charges past the enable threshold 2. place a resistor from vdd to enable. this causes more current to flow in the shutdown mode, but does not delay converter startup. if a resistor is used, the total current into the enable pin should be limited to no more than 500 a. the enable pin is self-clamping. the clamp voltage can be as low as 1 v with a 1-k ground impedance. due to this self-clamping feature, the pull-up impedance on the enable pin should be selected to limit the sink current to less than 500 a. driving the enable pin with a low-impedance source voltage can result in damage to the device. because of the self-clamping feature, it requires care when connecting multiple enable pins together. for enabling multiple tps4019x devices (tps40190, tps40192, tps40193, tps40195, tps40197), see the application report slva509 . 4 1 5 7 0? 200 ? 200 n? 1 n? 1 n? 300 n? to enable chip vdd enable gnd
11 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated feature description (continued) 7.3.5 startup sequence and timing after input power is applied, the 5-v onboard regulator comes up. once this regulator comes up, the device goes through a period where it samples the impedance at the comp pin and determines the short circuit protection threshold voltage, by placing 400 mv on the comp pin for approximately 1 ms. during this time, the current is measured and compared against internal thresholds to select the short circuit protection threshold. after this, the comp pin is brought low for 1 ms. this ensures that the feedback loop is preconditioned at startup and no sudden output rise occurs at the output of the converter when the converter is allowed to start switching. after these initial two milliseconds, the internal soft-start circuitry is engaged and the converter is allowed to start. see figure 13 . figure 13. startup sequence 7.3.6 selecting the short circuit current a short circuit in the devices is detected by sensing the voltage drop across the low-side mosfet when it is on, and across the high-side mosfet when it is on. if the voltage drop across either mosfet exceeds the short circuit threshold in any given switching cycle, a counter increments one count. if the voltage across the high-side mosfet was higher that the short circuit threshold, that mosfet is turned off early. if the voltage drop across either mosfet does not exceed the short circuit threshold during a cycle, the counter is decremented for that cycle. if the counter fills up (a count of 7) a fault condition is declared and the drivers turn off both mosfets. after a timeout of approximately 50 ms, the controller attempts to restart. if a short circuit is still present at the output, the current quickly ramps up to the short circuit threshold and another fault condition is declared and the process of waiting for the 50 ms an attempting to restart repeats. the low-side threshold increases as the low- side on time decreases due to blanking time and comparator response time. see figure 11 for changes in the threshold as the low-side mosfet conduction time decreases. these devices provide three selectable short circuit protection thresholds for the low-side mosfet: 100 mv, 200 mv and 280 mv. the particular threshold is selected by connecting a resistor from comp to gnd. table 1 shows the short circuit thresholds for corresponding resistors from comp to gnd. when designing the compensation for the feedback loop, remember that a low impedance compensation network combined with a long network time constant can cause the short circuit threshold setting to not be as expected. the time constant and impedance of the network connected from comp to fb should be as in equation 1 to ensure no interaction with the short circuit threshold setting. v enable v comp v out sc threshold configured (1 ms) soft start time (4 ms) compensation network zeroed (1 ms) udg-06062
12 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated feature description (continued) where ? t is 1 ms, the sampling time of the short circuit threshold setting circuit ? r1 and c1 are the values of the components in figure 14 (1) figure 14. short circuit threshold feedback network table 1. short circuit threshold voltage selection comparator resistance r comp (k ? ) current limit threshold voltage (mv) v ilim (v) 12 10% 280 open 200 4 10% 100 the range of short circuit current thresholds that can be expected is shown in equation 2 and equation 3 . (2) where ? i scp is the short circuit current ? v ilim is the short circuit threshold for the low-side mosfet ? r ds(on) is the channel on-resistance of the low-side mosfet (3) due to blanking time considerations, overcurrent threshold accuracy may fall off for duty cycle greater than 75% with the tps40192, or 88% with the tps40193. specifically, the overcurrent comparator has only a very short time to sample the sw pin voltage under these conditions. as a result, the comparator may not have time to respond to voltages very near the threshold. the short circuit protection threshold for the high-side mosfet is fixed at 550 mv typical, 400 mv minimum. this threshold is in place to provide a maximum current output using pulse by pulse current limit in the case of a fault. the pulse terminates when the voltage drop across the high-side mosfet exceeds the short circuit threshold. the maximum amount of current that can be specified to be sourced from a converter is found by equation 4 . i scp : min ; = v ilim : min ; r ds : on ; max i scp : max ; = v ilim : max ; r ds : on ; min 2 c1 r1 c2 3 comp tps40192 tps40193 fb v out r comp 0.4 v r1 e @ f t r1c1 a < 10 a
13 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated where ? i out(max) is the maximum current that the converter is specified to source ? v ilimh(min) is the short circuit threshold for the high-side mosfet (400 mv) ? r ds(on)max is the maximum resistance of the high-side mosfet (4) if the required current from the converter is greater than the calculated i out(max) , a lower resistance high-side mosfet must be chosen. both the high-side and low-side thresholds use temperature compensation to approximate the change in resistance for a typical power mosfet. this helps to counteract shifts in overcurrent thresholds as temperature increases. for this feature to be effective, the mosfets and the device must be well coupled thermally. 7.3.7 5-v regulator an on board 5-v regulator that allows the parts to operate from a single voltage feed. no separate 5-v feed to the part is required. this regulator needs to have a minimum of 1- f of capacitance on the bp5 pin for stability. a ceramic capacitor is suggested for this purpose. this regulator can also be used to supply power to nearby circuitry, eliminating the need for a separate ldo in some cases. if this pin is used for external loads, be aware that this is the power supply for the internals of the tps40192 and tps40193 devices . while efforts have been made to reduce sensitivity, any noise induced on this line has an adverse effect on the overall performance of the internal circuitry and shows up as increased pulse jitter, or skewed reference voltage. also, when the device is disabled by pulling the en pin low, this regulator is turned off and cannot supply power. the amount of power available from this pin varies with the size of the power mosfets that the drivers must operate. larger mosfets require more gate drive current and reduce the amount of power available on this pin for other tasks. the total current that this pin can draw from both the gate drive and external loads cannot exceed 50 ma. the device uses up to 4 ma from the regulator and the total gate drive current can be found from equation 5 . for regulator stability, a 1- f capacitor is required to be connected from bp5 to gnd. in some applications using higher gate charge mosfets, a larger capacitor is required for noise suppression. for a total gate charge of both the high and low-side mosfets greater than 20 nc, a 2.2- f or larger capacitor is recommended. where ? i g is the required gate drive current ? f sw is the switching frequency (600 khz for tps40192, and 300 khz for tps40193) ? q g(high) is the gate charge requirement for the high-side mosfet when v gs = 5 v ? q g(low) is the gate charge requirement for the low-side mosfet when v gs = 5 v (5) 7.3.8 prebias start-up the tps40192 and tps40193 devices contains a unique circuit to prevent current from being pulled from the output during startup in the condition the output is pre-biased. when the soft-start commands a voltage higher than the pre-bias level (internal soft-start becomes greater than feedback voltage [v fb ]), the controller slowly activates synchronous rectification by starting the first ldrv pulses with a narrow on-time. it then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-d), where d is the duty cycle of the converter. this scheme prevents the initial sinking of the pre-bias output, and ensures that the out voltage (v out ) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre- biased startup to normal mode operation with minimal disturbance to the output voltage. the amount of time from the start of switching until the low-side mosfet is turned on for the full (1-d) interval is defined by 32 clock cycles. i g = f sw k q g : high ; + q g : low ; o i out : max ; = v ilim : min ; r ds : on ; max
14 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 7.3.9 drivers the drivers for the external hdrv and ldrv mosfets are capable of driving a gate-to-source voltage of 5 v. the ldrv driver switches between vdd and gnd, while hdrv driver is referenced to sw and switches between boot and sw. the drivers have non-overlapping timing that is governed by an adaptive delay circuit to minimize body diode conduction in the synchronous rectifier. the drivers are capable of driving mosfets that are appropriate for a 15-a (tps40192) or 20-a (tps40193) converter. 7.3.10 power good the tps40192 and tps40193 devices provides an indication that output power is good for the converter. this is an open drain signal and pulls low when any condition exists that would indicate that the output of the supply might be out of regulation. these conditions include: ? v fb is more than 10% from nominal ? soft-start is active ? an undervoltage condition exists for the device ? a short circuit condition has been detected ? die temperature is over (145 c) note when there is no power to the device, pgood is not able to pull close to gnd if an auxiliary supply is used for the power good indication. in this case, a built in resistor connected from drain to gate on the pgood pull down device makes the pgood pin look approximately like a diode to gnd. 7.3.11 thermal shutdown if the junction temperature of the device reaches the thermal shutdown limit of 145 c, the pwm and the oscillator are turned off and the hdrv pin and the ldrv pin are driven low, turning off both fets. when the junction cools to the required level (125 c nominal), the pwm inititates soft start as during a normal power up cycle. 7.4 device functional modes 7.4.1 continuous conduction mode the tps40192 and tps40193 devices devices operate in continuous conduction mode, regardless of the output current. following the first 32 cycles, during which the low-side mosfet on-time is slowly increased to prevent current sinking due to a pre-biased output, the high-side mosfet and low-side mosfet on-times are fully complementary. 7.4.2 low-quiescent shutdown when the enable pin of the tps40192, and tps40193 devices is held below 0.6 v, the device enters a low quiescent current shutdown mode, drawing only 45 a typically from the vdd pin.
15 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information this example illustrates the design process and component selection for a 12 v to 1.8 v point-of-load synchronous buck regulator using the tps40192. a definition of symbols used can be found in table 7 of this datasheet. 8.2 typical application figure 15. tps40192 design example schematic 1 2 3 4 10 9 8 7 hdrv sw boot ldrv enable fb comp vdd u1 tps40192drc 5 6 bp5 pgd gnd c6 470 nf l1 1.0 h c8 2 100 f r11 0 ? q3 irf7834 q2 irf7466 c7 2 10 f c11 1.0 f r12 100 n? c5 4.7 f c4 1.0 f pgood r4 100 n? r6 4.22 n? c3 10 nf c1 100 pf r9 3.9 n? r8 20 n? r10 2.61 n? c2 1000 pf r7 9.76 n? r1 5.1 n? r2 2 n? q1 2n7002w v in 12 v (8 v to 14 v) v in + v in disable v out 1.0 v 10 a v out + v out power ground signal ground r14 100 n? r13 0 ? copyright ? 2016, texas instruments incorporated
16 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated typical application (continued) 8.2.1 design requirements the requirements for this design are summarized in table 2 . table 2. design requirements parameter notes and conditions min nom max units input characteristics v in input voltage 8 12 14 v i in input current v in = 8 v, i out = 10 a 2.7 2.85 a no load input current v in = 8 v, i out = 0 a 48 60 ma vin_uvlo input uvlo 0 a i out 10 a 3.9 4.2 4.4 v output characteristics v out output voltage v in = 12 v, i out = 6 a 1.8 v line regulation 8 v v in 14 v, i out = 6 a 0.5% load regulation v in = 12 v, 0 a i out 10 a 0.5% v out(ripple) output voltage ripple v in = 12 v, i out = 10 a 40 mvpp i out output current 8 v v in 14 0 6 10 a i ocp output overcurrent inception point v in = 12 v, vout = vout-5% 19 a transient response i load step 0.75 x i out(max) to 0.25 i out(max) 5 a load slew rate 5 a/ sec overshoot 50 mv systems characteristics f sw switching frequency 480 600 720 khz pk peak efficiency v in = 8 v, 0 a i out 10 a 89% full-load efficiency v in = 8 v, i out 10 a 86% t j operating temperature range 8 v v in 14 v, 0 a i out 10 a -40 25 60 c 8.2.2 detailed design procedure 8.2.2.1 selecting the switching frequency choose a switching f sw of 600 khz to reduce the required inductor and capacitor sizes. 8.2.2.2 inductor selection the inductor is typically sized for approximately 30% peak-to-peak ripple current (i ripple ). given this target ripple current, the required inductor size can be calculated by equation 6 . (6) a standard value of 1.0 h is selected. solving for i ripple using an inductor value of 1.0 h, results in 2.6-a peak-to-peak ripple. the rms current through the inductor is approximated by equation 7 . (7) using equation 7 , the maximum rms current in the inductor is approximately 10.03 a i l : rms ; = k i l : avg ; o 2 + 1 12 : i ripple ; 2 = : i out ; 2 + 1 12 : i ripple ; 2 = : 10 a ; 2 + 1 12 : 2.6 a ; 2 n 10.03 a l n v in : max ; f v out i ripple v out v in : max ; 1 f sw = 14 v f 1.8 v 0.3 10 a 1.8 v 14 v 1 600 khz = 0.87 h
17 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 8.2.2.3 output capacitor selection (c8) the selection of the output capacitor is typically driven by the output transient response. the equation 8 and equation 9 overestimate the voltage deviation to account for delays in the loop bandwidth and can be used to determine the required output capacitance. (8) if ? v in(min) > 2 v out , use overshoot to calculate minimum output capacitance. ? v in(min) < 2 v out , use undershoot to calculate minimum output capacitance. (9) (10) with a minimum capacitance, the maximum allowable esr is determined by the maximum ripple voltage and is approximated by equation 11 . (11) two 1206 100- f, 6.3-v x5r ceramic capacitors are selected to provide more than 178- f of minimum capacitance and less than 4.4 m ? of esr (2.5 m ? each). 8.2.2.4 peak current rating of the inductor with output capacitance, it is possible to calculate the charge current during start-up and determine the minimum saturation current rating for the inductor. the start-up charging current is approximated by equation 12 . (12) (13) table 3. inductor requirements parameter symbol value units inductance l 1.0 h rms current (thermal rating) i l(rms) 10.03 a peak current (saturation rating) i l(peak) 11.4 a pg0083.102 1.0- h is selected for its small size, low dcr (6.6 m ? ) and high current handling capability (12 a thermal, 17 a saturation) 8.2.2.5 input capacitor selection (c7) the input voltage ripple is divided between capacitance and esr. for this design v ripple(cap) = 400 mv and v ripple(esr) = 200 mv. use equation 14 to estimate the minimum capacitance and maximum esr. (14) i l : peak ; = i out : max ; + l 1 2 i ripple p + i charge = 10 a + l 1 2 2.6 a p + 120 ma = 11.4 a i charge = v out c out t ss = 1.8 v 200 f 3.0 ms = 120 ma esr max < v ripple : tot ; f v ripple : cap ; c out = v ripple : tot ; f l i ripple c out b sw p i ripple = 36 mv f @ 2.6 a 178 f 600 khz a 2.6 a = 4.4 ? c out : min ; = k i tran : max ; o 2 l v out v over = : 4 a ; 2 1.0 h 1.8 v 50 mv = 178 f v under < i tran c out ? t = i tran c out i tran l : v in f v out ; = : i tran ; 2 l : v in f v out ; c out v over < i tran c out ? t = i tran c out i tran l v out = : i tran ; 2 l v out c out c in : min ; = i out v out v ripple : cap ; v in (min ) f sw = 10 a 1.8 v 400 mv 8 v 600 khz = 9.375 j f
18 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (15) for this design c in(min) > 9.375 f and esr < 17.7 m ? . use equation 16 to estimate the rms current in the input capacitors. (16) the total input capacitance must support 2.37 a of rms ripple current. two 1210 10- f, 25 v, x5r ceramic capacitors with approximately 2 m ? esr and a 2-a rms current rating are selected. higher voltage capacitors minimize capacitance loss at the dc bias voltage to ensure the capacitors have sufficient capacitance at the working voltage. 8.2.2.6 mosfet switch selection (q1, q2) the switching losses for the high-side mosfet are estimated by equation 17 . (17) switching losses in this design are highest at high-line. designing for 1 w of total loss in each mosfet and 60% of the total high-side mosfet losses in switching losses, estimate the maximum gate-drain charge for the design by using equation 18 . (18) the switching losses of the synchronous rectifier are lower than the switching losses of the main mosfet because the voltage across the mosfet at the point of switching is reduced to the forward voltage drop across the body diode of the sr mosfet and are estimated by using equation 19 . the conduction losses in the main mosfet are estimated by the rms current through the mosfet times its r ds(on) . (19) estimating about 40% of total mosfet losses to be high-side conduction losses, the maximum r ds(on) of the high-side mosfet can be estimated by using equation 20 . (20) estimating 80% of total low-side mosfet losses in conduction losses, repeat the calculation for the synchronous rectifier, whose losses are dominated by the conduction losses. calculate the maximum r ds(on) of the synchronous rectifier by equation 21 . (21) i rms : cin ; = i in : rms ; f i in : avg ; = l i out + 1 12 i ripple p v out v in f v out i out v in = l 10 a + 1 12 2.6 a p 1.8 v 14 v f 1.8 v 10 a 14 v = 2.37 a esr max = v ripple : esr ; i out + @ 1 2 i ripple a = 200 mv 10 a + @ 1 2 2.6 a a = 17.7 ? r ds : on ; q2_max = p q2con k i l : rms ; o 2 @ 1 f v out v in a = 800 mw 10.03 2 @ 1 f 1.8 v 14 v a = 9.1 m 3 r ds : on ; q1 ,max = p q1con k i l : rms ; o 2 v out v in = 400 mw : 10.03 a ; 2 1.8 v 14 v = 30.9 m 3 p g1 : con ; = i l : rms ; r ds : on ; q1 v out v in q gd1 (max ) = p g1sw v in i out v drv f v th r drv 1 f sw = 600 mw 14 v 10 a 5 v f 2 v 2.5 3 1 600 khz = 8.6 nc p g1sw = 1 2 v in i out t sw b sw = 1 2 v in i out q gd1 v drv f v th r drv b sw
19 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated table 4. power mosfet requirements parameter symbol value units high-side mosfet on-resistance r ds(on)q1 30.9 m ? high-side mosfet gate-to-drain charge q gd1 8.5 nc low-side mosfet on-resistance r ds(on)q2 8.8 m ? the irf7466 has an r ds(on)max of 30.9 m ? at 4.5-v gate drive and only 8.0-nc v gd "miller" charge with a 4.5-v gate drive, and is chosen as a high-side mosfet. the irf7834 has an r ds(on)q1,max of 5.5 m ? at 4.5-v gate drive and 44 nc of total gate charge. these two fets have maximum total gate charges of 23 nc and 44 nc respectively, which draws 40.2-ma from the 5-v regulator, less than its 50-ma minimum rating. 8.2.2.7 boot strap capacitor to ensure proper charging of the high-side mosfet gate, limit the ripple voltage on the boost capacitor to less than 50 mv. (22) use the next higher standard value of 470 nf for the value of the bootstrap capacitor. note it is recommended to add a high-resistance resistor in parallel with the bootstrap capacitor. adding a small amount of load to the bootstrap capacitor (100 k for a 100-nf typical capacitor) creates a discharge time constant for the bootstrap voltage following a shutdown event. this prevents the possibility of an inadvertent turn-on of the high-side mosfet following shutdown via the enable pin, due to leakage paths within the driver stage which can slowly transfer the bootstrap voltage to the hdrv pin following the shutdown. (see figure 15 ) 8.2.2.8 input bypass capacitor (c6) as suggested, select a 1.0- f ceramic bypass capacitor for vdd. 8.2.2.9 bp5 bypass capacitor (c5) the recommended minimum 1.0- f ceramic capacitance stabilizes the 5-v regulator. to limit regulator noise to less than 10 mv, the bypass capacitor is sized by using equation 23 . (23) because the q2 gate charge is larger than q1 and the total gate charge of q2 is 44 nc, a bp5 capacitor of 4.4- f is calculated, and the next larger standard value of 4.7 f is selected to limit noise on the bp5 regulator. 8.2.2.10 input voltage filter resistor (r11) because the minimum input voltage (v in(min) ) is greater than 6.0 v, place a 0- ? resistor in the vdd resistor location. if v in(min) was < 6.0 v, an optional series vdd resistor with a value between 1 ? and 2 ? filters switching noise from the device. limit the voltage drop across this resistor to less than 50 mv. (24) driving the two fets with 23 nc and 44 nc respectively, the maximum i vdd current calculation of 43 ma yields a resistor value of approximately 1 ? . 8.2.2.11 short circuit protection (r9) the devices use the negative drop across the low-side mosfet during the off time to measure the inductor current. equation 25 approximates the voltage drop across the low-side mosfet. r vdd = v rvdd : max ; i dd = 50 mv 3 ma + (q g1 ,tot + q g2 ,tot ) b sw = 50 mv 3 ma + : 44 nc + 23 nc) 600 khz ; = 50 mv 43 ma 1 c bp5 = 100 max : q g1 , q g2 ; = 100 max : 23 nc, 44 nc ; 4.4 f c boost = 20 q g1 = 20 23 nc = 460 nf
20 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (25) the internal temperature coefficient of the tps40192 device helps compensate for the mosfet on-resistance (r ds(on) ) temperature coefficient. for this design select the short circuit protection voltage threshold of 110 mv by selecting r9 = 3.9 k ? . 8.2.2.12 feedback compensation (modeling the power stage) the dc gain of the modulator is given by equation 26 . (26) because the peak-to-peak ramp voltage given in the electrical characteristics table is projected from the ramp slope over a full switching period, the modulator gain can be calculated as equation 27 . the maximum modulator gain for this design is found to be 14 (23.0 db). (27) the l-c filter applies a double pole at the resonance frequency described in equation 28 . (28) at any frequency lower than this ( 11.3 khz), the power stage has a dc gain of 23 db and at any higher frequency the power stage gain drops off at -40 db per decade. the esr zero is approximated in equation 29 . (29) using two 100 f, 2.5 m esr ceramic output capacitors, the calculated f esr of 636 khz is greater than 1/5th the switching frequency, and therefore outside the scope of the error amplifier design. the gain of the power stage would change to ? 20 db per decade above f esr . the straight line approximation the power stage gain is described in figure 16 . the following compensation design procedure assumes f esr > f res . for designs using large high-esr bulk capacitors on the output where f esr < f res . type-ii compensation can be used but is not described in this data sheet. . figure 16. approximation of power stage gain figure 17. type-iii compensator used with tps40040 or tps40041 8.2.2.13 feedback divider (r7, r8) select a value for r8 between 10 k ? and 100 k ? . for this design, select 20 k ? . r7 is then selected to produce the desired output voltage when v fb = 0.591 v using equation 30 . v cs (max ) = i l : peak ; r ds : on ; ,q2 ,max = 11.4 a 5.5 m 3 62.7 mv gain a mod f esr 0 db f res 40 db/decade 20 db/decade frequency (log scale) + c3 2 + v fb 3 pad r6 c1 to pwm v out r7 r10 r8 c2 f esr = 1 t n c out r esr = 1 t n : 2 100 f ; @ 2.5 m 2 a = 636 khz f res = 1 t n ? l c = 1 t n 1 h 200 f 11.3 khz a mod (max ) = v in (max ) v ramp : pp ; = 14 v 1 v pp = 14 a mod = @ v out @ v comp = @ d v comp v in = @ t @ v ramp 1 t sw v in
21 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (30) select the closest standard value of 9.76 k ? . a slightly lower nominal value increases the nominal output voltage slightly to compensate for some trace impedance at load. 8.2.2.14 error amplifier compensation (r6, r10, c1, c2, c3) place two zeros at 50% and 100% of the resonance frequency to boost the phase margin before resonance frequency generates ? 180 of phase shift. for f res = 11.7 khz, f z1 = 5.8 khz and f z2 = 11 khz. selecting the crossover frequency (f co ) of the control loop between 3 times the lc filter resonance and 1/5th the switching frequency. for most applications 1/10th the switching frequency provides a good balance between ease of design and fast transient response. ? if f esr < f co ; f p1 = f esr and f p2 = 4 f co ? if f esr > 2 f co ; f p1 = f co and f p2 = 8 f co . for this design ? f sw = 600 khz ? f res = 11.7 khz ? f esr = 636 khz ? f co = 60 khz and because ? f esr > 2 f co , f p1 = f co = 60 khz and f p2 = 4 f co = 500 khz. because f co < f esr the power stage gain at the desired crossover can be approximated in equation 31 . (31) table 5. error amplifier design parameters parameter symbol value units first zero frequency f z1 5.8 khz second zero frequency f z2 11.0 first pole frequency f p1 60 second pole frequency f p2 500 midband gain a mid(band) 1.86 v/v approximate c2 with the formula described in equation 32 . (32) for a calculated value for c2 of 723 pf, the closest standard capacitor value is 1000 pf. approximate r10 using equation 33 . (33) for a calculated value for r10 of 2.65 k ? , the closest standard resistor value is 2.61 k ? . calculate r6 using equation 34 . (34) for a calculated value for r6 of 4.29 k ? , the closest standard resistor value is 4.22 k ? . calculate c1 and c3 using equation 35 and equation 36 . (35) c3 = 1 t n r6 f z1 = 1 t n 4.22 k 5.8 khz = 6.5 nf r6 = a mid (band ) r10 r8 r10 + r8 = 1.86 2.61 k 3 20 k 3 2.61 k 3 + 20 k 3 = 4.29 k r10 = 1 t n c2 f p1 = 1 t n 1000 pf 60 khz = 2.65 k c2 = 1 t n r8 f z2 = 1 t n 20 k 3 11 khz = 723 pf a ps (fco ) = a mod (dc ) f 40 log l f co f res p = 10 aps ( fcc )/20 = 10 5.4 db /20 = 1.86 r7 = v fb r8 v out f v fb = 0.591 v 20 k 1.8 v f 0.591 v = 9.78 k
22 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (36) using the a standard value close to 75 pf, select c1 = 100 pf. likewise, using a standard value close to 6.5 nf, select c3 = 10 nf. the error amplifier straight line approximation transfer function is described in figure 18 . figure 18. error amplifier transfer function approximation 8.2.3 application curves figure 19. efficiency vs. output current figure 20. output voltage regulation 60 65 90 95 0 2 4 10 6 8 load current (a) efficiency (%) 70 75 85 80 input voltage (v) 14 12 8 input voltage (v) 14 12 8 1.810 1.8105 1.8125 1.813 0 2 4 10 6 8 load current (a) output voltage (v) 1.811 1.8115 1.812 f p2 f p1 frequency (log scale) gain a mid(band) 0 db f z2 f z1 c1 = 1 t n r6 f p2 = 1 t n 4.22 k 500 khz = 75 pf
23 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated figure 21. output voltage ripple figure 22. switching waveforms 9 power supply recommendations the tps40192, and tps40193 devices are designed to operate from a supply on the vdd pin, ranging from 4.5 v to 18 v. this supply must be well regulated and bypassed for proper operation of the devices. the vdd pin must be connected to the same supply as the power stage conversion input voltage for accurate high-side current sensing. the bp5 pin is the output of an internal low dropout regulator which is used to supply the gate drive voltages, and must also have good local bypassing for proper operation of the devices.
24 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 10 layout 10.1 layout guidelines ? optionally use r11 as a vdd filter resistor ? locate the bypass capacitors (c7) near the power mosfets. ? terminate signal components to a signal ground island separate from power ground ? connect signal ground island to thermal pad with a single 10-mil wide trace. ? connect power ground to the source of the synchronous rectifier. ? the thermal pad serves as the only ground for the controller. ? powerpad must be connected to signal ground and power ground at a single point only. connect the powerpad to the system ground. ? powerpad ? should be directly connected to sync mosfet (q3) source with short, wide trace. ? locate 3-5 vias in powerpad ? land to remove heat from the device. ? connect input capacitors (c7 and c9) and output capacitors (c8 andc10) grounds directly to sync mosfet (q3) source with wide copper trace or solid power ground island. ? locate input capacitors (c7 and c9), mosfets (q2 and q3), inductor (l1) and output capacitor (c8 andc10) over power ground island. ? use short, wide traces for ldrv and hdrv mosfet connections. ? route sw trace near hdrv trace. ? route gnd trace near ldrv trace. ? use separate analog ground island under feedback components (c1, c2, c3, r5, r6, r7, r8 and r10). ? connect ground islands at powerpad ? with 10-mil wide trace opposite sync mosfet (q2) source connection. 10.2 layout examples figure 23. tps40192 and tps40193 devices sample layout - component placement and top side copper
25 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated layout examples (continued) figure 24. tps40192 and tps40193 devices sample layout - bottom side copper (x-ray view from top)
26 tps40192 , tps40193 slus719f ? march 2007 ? revised november 2016 www.ti.com product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 11 device and documentation support 11.1 device support 11.1.1 development support 11.1.1.1 related devices the following devices have characteristics similar to the tps40192 and tps40193. table 6. related devices device description tps40100 midrange input synchronous controller with advanced sequencing and output margining tps40075 wide input synchronous controller with voltage feed forward tps40190 low pin count synchronous buck controller 11.1.2 device nomenclature table 7. definition of symbols symbol description v in(max) maximum operating input voltage v in(min) minimum operating input voltage v in(ripple) peak- to-peak ac ripple voltage on v in v out target output voltage v out(ripple) peak- to-peak ac ripple voltage on v out i out(max) maximum operating load current i ripple peak-to-peak ripple current through inductor i l(peak) peak current through inductor i l(rms) root mean squared current through inductor i rms(cin) root mean squared current through input capacitor f sw switching frequency f co desired control loop crossover frequency a mod low frequency gain of the pwm modulator ( v out / v control ) v control pwm control voltage (error amplifier output voltage v comp ) f res l-c filter resonant frequency f esr output capacitor esr zero frequency f p1 first pole frequency in error amplifier compensation f p2 second pole frequency in error amplifier compensation f z1 first zero frequency in error amplifier compensation f z2 second pole frequency in error amplifier compensation q g1 total gate charge of main mosfet q g2 total gate charge of synchronous rectifier mosfet r ds(on)q1 "on" drain-to-source resistance of main mosfet r ds(on)q2 "on" drain-to-source resistance of synchronous rectifier moseft p q1c(on) conduction losses in main switching mosfet p q1sw switching losses in main switching mosfet p q2c(on) conduction losses in synchronous rectifier mosfet q gd gate-to-drain charge of synchronous rectifier mosfet q gs gate-t-source charge of synchronous rectifier mosfet
27 tps40192 , tps40193 www.ti.com slus719f ? march 2007 ? revised november 2016 product folder links: tps40192 tps40193 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 11.2 documentation support access these reference documents as well as design tools and links to additional references, including design software at www.power.ti.com . ? under the hood of low voltage dc/dc converters , sem1500 topic 5, 2002 seminar series ? understanding buck power stages in switchmode power supplies , march 1999 ? design and application guide for high speed mosfet gate drive circuits , sem 1400, 2001 seminar series ? designing stable control loops , sem 1400, 2001 seminar series ? powerpad ? thermally enhanced package application report ? powerpad ? made easy application report ? qfn/son pcb attachment application report 11.3 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 8. related links parts product folder sample & buy technical documents tools & software support & community tps40192 click here click here click here click here click here tps40193 click here click here click here click here click here 11.4 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.5 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.6 trademarks e2e is a trademark of texas instruments. 11.7 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.8 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 15-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples hpa00351drcr active vson drc 10 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 0193 tps40192drcr active vson drc 10 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 0192 tps40192drct active vson drc 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 0192 tps40192drctg4 active vson drc 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 0192 TPS40193DRCR active vson drc 10 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 0193 TPS40193DRCRg4 active vson drc 10 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 0193 tps40193drct active vson drc 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 0193 tps40193drctg4 active vson drc 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 0193 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 15-apr-2017 addendum-page 2 (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps40192drcr vson drc 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 tps40192drct vson drc 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 tps40192drct vson drc 10 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 q2 TPS40193DRCR vson drc 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 tps40193drct vson drc 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 package materials information www.ti.com 11-mar-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps40192drcr vson drc 10 3000 367.0 367.0 35.0 tps40192drct vson drc 10 250 210.0 185.0 35.0 tps40192drct vson drc 10 250 195.0 200.0 45.0 TPS40193DRCR vson drc 10 3000 367.0 367.0 35.0 tps40193drct vson drc 10 250 210.0 185.0 35.0 package materials information www.ti.com 11-mar-2017 pack materials-page 2

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